Method for suppressing transient enhanced diffusion of dopants in silicon

ABSTRACT

Method for suppressing the transient enhanced diffusion (TED) of a dopant implanted in a thin surface layer of a semiconductor substrate, the TED being normally caused by the interaction between the dopant and the lattice damage caused by the implantation of the dopant itself or by pre-amorphization implantations during the post-implantation annealing thermal process. The aforesaid heat treatment is carried out on a crystalline semiconductor having an amorphous surface layer in which the dopant is implanted and having a layer rich in a trap element which effectively traps self-interstitial point defects. The layer rich in a trap element is spatially separated from the dopant-rich surface layer and is interposed between the dopant-rich surface layer and the interface between the amorphous and crystalline regions of the substrate.

The present invention relates in a general way to a process for theindustrial production of semiconductors and more particularly to amethod for treating semiconductors in order to suppress the transientenhanced diffusion (TED) caused by the interaction between the dopantand the damage to the lattice due to the implantation, this diffusionoccurring during the thermal process of post-implantation annealing.

The development of microelectronics has been stimulated and accompaniedby a reduction in the size of elementary devices. Continuing the trenddescribed in the last thirty years by the well-known Moore's Law, theRoadmap drawn up by the Semiconductor Industry Association [Road]requires the production, in the near future, of silicon devices havingelectrical junctions with depths of less than 30 nm, for which noeffective manufacturing methods have yet been found [Road].

Ion implantation is, and will probably continue for a long time to be,the preferred technique for introducing dopants into a siliconsubstrate. Conventionally, the junction depth is reduced by reducing theimplantation energy, causing a reduction in the thickness implanted withthe dopant. Theoretically, modern industrial implanters can providesufficiently shallow dopant profiles, by implanting with energies ofless than 1 keV. In practice, however, the junction depths which can beobtained are much greater than those predicted on the basis of theimplantation energy alone, owing to phenomena such as channelling(channelling of the implanted ions into the crystal matrix) andtransient enhanced diffusion (TED). TED is caused by the interactionbetween the dopant and the lattice damage caused by the implantation(self-interstitial point defects) during the thermal process of fastpost-implantation annealing (required for elimination of the damage andelectrical activation of the dopant), and is characterized by anincrease even of several orders of magnitude of the diffusivity of thedopant and a consequent considerable increase in the junction depth[Stolk, Napolitani].

TED makes it extremely difficult, if not impossible, to control thedistribution in depth of the dopant, and therefore the junction depth,simply by reducing the implantation energy. Moreover, the presence ofTED makes it necessary to reduce the implantation energy, thus reducingthe efficiency of the production lines for the devices (the currentobtainable in an implanter generally decreases with the energy) andincreasing production costs.

TED also causes a lateral enhanced diffusion of the dopant from thesource and drain regions (formed by ion implantation) towards the gateof a CMOS device, thus compromising the width of the gate in a way whichis difficult to control.

Effective methods of eliminating or reducing TED and channelling aretherefore required for the production of shallow junctions by ionimplantation in future generations of devices.

Pre-amorphization by ion implantation (by using non-electrically activespecies such as silicon, germanium and fluorine, for example) before theimplantation of the dopant completely eliminates the channelling tailsand eliminates the production of point defects by the implantation ofthe dopant. However, in addition to creating an amorphous surface layerin the crystalline substrate, the pre-amorphization implantation createsa large number of defects (particularly self-interstitial ones) beyondthe amorphous/crystalline interface (called end of range (EOR) defects),which, during the subsequent thermal processes of recrystallization andelectrical activation, diffuse towards the surface, interacting with thedopant and causing it to undergo transient enhanced diffusion [Jones,Robertson]. Although in some conditions the junctions produced bypre-amorphization implantation are shallower, usually this method,because of the significant TED and the large number of extended defectswhich it causes, cannot provide a solution for the formation ofextremely shallow junctions.

In the patent literature, EP-A-0 806 794 describes a method forproducing shallow doped regions in a semiconductor substrate bypre-amorphization and ion implantation; the method comprises thesub-amorphization implantation of a non-electrically active element suchas silicon or germanium before the implantation of a dopant. Theamorphization implantation energy is optimized to achieve the desireddopant profile.

U.S. Pat. No. 6,074,937 describes a process for producing high-densitysemiconductors, comprising shallow junctions in which lightly dopedregions are implanted in an amorphous region of the semiconductorsubstrate to reduce the TED in the subsequent activation heat treatment;before the activation heat treatment, a sub-surface non-amorphous regionis formed to eliminate the end of range (EOR) defects in thecrystallization of the amorphous region containing the lightly dopedregions.

U.S. Pat. No. 6,251,757 describes a process for fabricating a highlyactivated shallow doped junction in a semiconductor substrate, in whicha first implantation with silicon ions or germanium ions is carried outin a surface of the semiconductor substrate to form a pre-amorphizationjunction having a predetermined depth, and a subsequent implantationwith n- or p-type dopant is carried out at the pre-amorphizationjunction, after which the substrate is subjected to RTA (rapid thermalannealing) heat treatment to recrystallize the pre-amorphizationjunction.

EP-A-1 096 552 describes an implantation method designed to permit thecontrol of the effective dose even in ion implantation at extremely lowenergy, and comprising a first stage of pre-amorphization ionimplantation to produce an amorphous surface layer, a second stage ofcleaning the semiconductor surface to eliminate oxidized films, and athird stage of low-energy ion implantation for forming a shallowjunction.

The introduction of replacement carbon into the crystalline siliconmatrix, to make use of its property of trapping self-interstitials, isone method which has been developed to reduce TED [Stolk 95].

U.S. Pat. No. 6,153,920 describes a method for controlling the diffusionof atoms of dopant, such as boron, phosphorus and arsenic, implanted ina semiconductor substrate, which comprises the incorporation of carbonin a region of the substrate at a depth below the space-charge layer ofthe semiconductor device.

However, the presence of carbon in the active regions of the devices isundesirable, because it degrades the electrical properties of thematerial [Stolk 95, Ban] and complicates the electrical activation ofthe dopant [Priolo].

In the present state of the art, there is no way of eliminating TEDcompletely. The best developed method for producing shallow junctions isthat of pre-amorphization in suitable conditions, but at present thisdoes not enable sufficiently shallow junctions to be made for the mostadvanced technological nodes [Stolk 01]. A method for completelyeliminating TED could have important technological applications in thefield of semiconductors and the industrial treatment of semiconductors,and particularly in the formation of shallow junctions by ionimplantation and in the production of CMOS devices.

A first object of the invention is therefore a method for suppressingTED in a surface region having a certain thickness of a semiconductorsubstrate, as defined in the following claims. The method has twoobjectives:

-   a) complete suppression of TED;-   b) production of an electrically active doped surface region with a    negligible presence of undesired impurities.

Another subject of the invention, defined in the following claims,consists in a process for producing a semiconductor device, having ashallow doped region, by using the TED suppression method citedpreviously.

Further subjects of the invention are semiconductor devices which can beproduced by the methods and processes according to the invention, andalso a semiconductor device which can be used as an intermediate productfor making more complex semiconductor devices.

Further advantages and characteristics of the invention will be madeclear by the following detailed description, provided with reference tothe attached drawings and to a specific example of embodiment.

In the drawings,

FIG. 1: (a) schematic description of the experiment; transmissionelectron microscope (TEM) images of a cross section of the specimen withcarbon after heat treatment at 900° C. (b) and 1100° C. (c);

FIG. 2: profiles obtained by secondary ion mass spectroscopy (SIMS) of Bimplanted at 10 keV, dose 1×10¹⁴/cm² in pre-amorphized Si, before (x)and after (□) solid phase epitaxy (SPE), after SPE and rapid thermalannealing (RTA) at 900° C. for 30 seconds in a specimen with (◯) andwithout (●) C, and after SPE and RTA at 1.100° C. for 30 seconds in aspecimen with (Δ) and without (▴) C; the simulated profiles areillustrated as continuous lines, together with the mean diffusivity usedin the calculations;

FIG. 3: SIMS profiles of carbon before (continuous line) and after(dotted line) SPE, and after SPE and RTA at 900° C. for 30 seconds(dashed line) compared with the profile B after SPE and RTA at 900° C.(◯).

With reference to FIG. 1, a silicon substrate is prepared in such a wayas to have a surface region having a certain thickness A consisting ofamorphous silicon on top of the crystalline substrate. This region canbe produced, for example, by implanting silicon or germanium intocrystalline silicon, or by depositing amorphous silicon on top of asubstrate of crystalline silicon.

This substrate is prepared in such a way that it also has a surfaceregion of thickness B, smaller than the thickness A, which is rich indopant which has been introduced, for example by ion implantation beforeor after the forming of the amorphous layer. The effectiveness of theinvention is limited to the case of dopants whose diffusivity depends onthe concentration of self-interstitial point defects, these dopantsincluding, for example, boron (other relevant dopants having thischaracteristic are phosphorus and arsenic).

The method also comprises the introduction of a certain quantity of anelement X having the following properties:

-   -   a) it effectively traps self-interstitials;    -   b) it must be such that its diffusion can be kept at        insignificant values within a sufficiently wide surface region        throughout the process;

One example of an element with these properties is carbon.

The element X must be concentrated in a layer, namely the region D,interposed between the dopant-rich region and the interface between theamorphous and crystalline substances. The region D is thus spatiallyseparated from the dopant-rich region. X can be introduced, for example,by a suitable deposition carried out before the amorphizationimplantation, or by ion implantation (and heat treatments if required)before or after the amorphization implantation, or by ion implantationafter the deposition of an amorphous layer, or by deposition during thedeposition of the amorphous layer.

The material is then subjected to a cycle of heat treatments torecrystallize the amorphous layer. This process, performed in differentstages if required, is characterized by a thermal balance which is lowenough not to allow a significant migration of any excessself-interstitials which may be present in the material, and is alsosuch that it produces a negligible equilibrium diffusion of the dopantand of the element X. The result of this process, therefore, is therecrystallization of the material without the production of anydiffusion of the dopant or of the element X, and without significantdiffusion of any excess self-interstitials. The latter, if present, arelocated at the original amorphous/crystalline interface, in other wordsbeyond the layer rich in the element X.

This structure must be stable when exposed to subsequent heat treatmentswhich are required for the thermal activation of the dopant (therecrystallization process does not generally ensure complete activationof the dopant) or which are required by subsequent stage of theproduction of devices. In these heat treatments, the self-interstitialdefects normally diffuse towards the surface, causing TED of the dopantpresent in the region B.

The method proposed here consists in the total suppression of this flowof interstitials by means of the element X present in the region D. Thusa complete electrical activation of the dopant is achieved without anyundesired diffusion.

Owing to the complete suppression of the flow of self-interstitials bythe region D, there will be no anomalous diffusion of the element Xtowards the surface. This diffusion will therefore be the equilibriumdiffusion, and can be controlled by suitably optimizing the overallthermal process in such a way as to ensure an adequate spatialseparation between the region rich in the element X and the dopedregion.

The method can comprise the alternative embodiment in which therecrystallization and electrical activation of the dopant take place ina single thermal process.

The method can also comprise the case in which the substrate or partsthereof are made from silicon alloys, for example SiGe or SiGeC.

EXAMPLE

Molecular beam epitaxy (MBE) was used to grow on silicon a carbon(C)—enriched silicon layer with a thickness of 100 nm, acting as a trapelement with a C concentration of 2.4×10²⁰/cm³, corresponding to a totalC dose of 2.4×10¹⁵/cm². The layer was covered with a covering layer ofpure silicon with a thickness of 250 nm. During the growth, thetemperature of the substrate was held at 500° C. A second similarspecimen was grown without the C enrichment, as a control.

Both specimens were then amorphized from their surfaces to a depth ofapproximately 550 nm by ion implantation of Si with an energy of 250 keVand a dose of 3×10¹⁵/cm², at the temperature of liquid nitrogen, andwere then implanted with boron with an energy of 10 keV and a dose of1×10¹⁴/cm². After solid-phase epitaxy (SPE), carried out by annealing ina furnace at 450° C. for 30 minutes and at 700° C. for 30 minutes undera flow of nitrogen, the original structure was recovered with a goodcrystalline quality, as verified by Rutherford Back-scatteringSpectrometry-Channelling and with 100% of replacement C atoms, asverified by high-resolution X-ray diffraction analysis (HRXRD) and byresonant Back-scattering Spectrometry-Channelling analysis.

Finally, isochronal rapid thermal annealing (RTA) was carried out at 900and 1100° C. for 30 seconds on these specimens which had been subjectedto regrowth.

The chemical concentration depth profiles of C and B were thendetermined by secondary ion mass spectrometry (SIMS), using a CAMECAIMS-4f instrument, with an analysing beam of 3 keV O₂ ⁺ or 14.5 keV Cs⁺,collecting, respectively, secondary ions B⁺ or C⁻. The HRXRD (004)oscillation curves were determined by using a Philips MRD diffractometerin standard conditions (Bartels monochromator in Ge (220) setting, Cutube at 40 kV and 40 mA). The activation of the dopant in the specimenswas evaluated by measuring the sheet resistance with a four-point probeapparatus. The extended defects caused by the pre-amorphizationimplantation were characterized by transmission electron microscopy(TEM).

The excess interstitials left beyond the original amorphous-crystallineinterface after the SPE cycle will develop into complex agglomeratesduring the subsequent RTA process. The formation and dissolution of theaforesaid defects will maintain a flow of interstitials towards thesurface for a certain time, causing TED of the boron implanted near thesurface. In the experiment which was conducted, the layer rich inreplacement carbon was positioned between the EOR damage and the boron,in such a way as to trap the interstitials flowing towards the surfaceand consequently to suppress the TED.

FIGS. 1 b and 1 c show the TEM images of the cross section of thecarbon-containing specimen, after annealing at 900° C. and at 1100° C.respectively. After 30 seconds at 900° C., there was completedissolution of the {311} defects (FIG. 1 b) which are the mostsignificant source of interstitials inducing TED. However, a largenumber of dislocation loops of the interstitial type were stillobserved; these can act as reservoirs for a large number ofinterstitials. These defects are completely dissolved after 30 secondsat 1100° C., to the extent that no more EOR defects are visible (FIG. 1c).

These defects are known to be highly stable and capable of storing theexcess interstitials without releasing them, even after aggressive heattreatment processes at 1000° C., and thus their presence would notconstitute a problem for CMOS planar technology. RTA treatment at 1100°C. was carried out in order to verify the capacity of the C-rich layerto block the interstitials until the dissolution of the EOR defects wascomplete.

FIG. 2 shows the SIMS concentration profiles of boron implanted with anenergy of 10 keV, at a dose of 1×10¹⁴/cm² in pre-amorphized siliconbefore and after SPE for the carbon-containing specimen (identicalprofiles were found for the control specimen) and after SPE with theaddition of RTA at 900° C. or 1100° C. for 30 seconds both for thecarbon-containing specimen and for the control specimen. As shown inFIG. 2, all the profiles after RTA were also simulated in a satisfactoryway by solving the Fick's law equation, using as the initial data theprofile measured by SIMS after SPE and taking as the free parameter adiffusion coefficient which is constant with time and depth. Withoutcarbon, the dissolution of the {311} defects causes significant TED. Forexample, as shown in FIG. 2, the diffusion in the control specimen wassimulated in a satisfactory way for the RTA process carried out for 30seconds at 900° C., assuming a mean diffusivity greater by a factor of30±10 than the equilibrium value.

As demonstrated in FIG. 2, the presence of carbon has a significanteffect on the diffusion of the boron. The profile after 900° C., in thepresence of the carbon-rich layer, compatibly with the equilibriumdiffusion, is not distinguishable from the specimen after SPE. Thus acarbon-rich silicon layer with a C dose of 2.4×10¹⁵/cm² completelysuppresses the TED produced by the complete dissolution of {311} defectsof the EOR damage. This, combined with the fact that the diffusionduring SPE is extremely low, results in a limited widening of theprofile during the whole process (in other words from the specimenimmediately after implantation to the specimen after SPE and RTA),causing a widening of less than 3 nm at a concentration level of1×10¹⁷/cm³.

The profiles in FIG. 2 after 30 seconds at 1100° C. show what happensafter complete dissolution of the EOR defects. A very high diffusion wasobserved in the specimen without C, supported by the completedissolution of the EOR damage. The increase in diffusion during RTA for30 seconds at 1100° C. was estimated to be 3.6±0.5. In this case also,the introduction of the C significantly suppresses the diffusion, asshown by the specimen with C, where the increase in diffusion was0.9±0.2, in other words the mean diffusivity is compatible with theequilibrium value. Thus the C-rich layer completely prevents the flow ofinterstitials, also generated by the total dissolution of the EORdamage.

In order to produce a shallow junction, the B must be electricallyactive. An analysis was carried out with a four-point probe, in order tomeasure the sheet resistance and thus evaluate the activation of thedopant. If it was completely active, the boron in the C-containingspecimen after SPE or after SPE and RTA at 900° C. would produce a sheetresistance of approximately 830 Ω/□. After SPE, a value of 1240 Ω/□ wasfound, indicating that the process of regrowth was not sufficient tocompletely activate the B. On the other hand, complete electricalactivation was reached after SPE followed by RTA at 900° C. for 30seconds, in which case a sheet resistance of 850±50 Ω/□ was found.

The question is whether the carbon-rich layer will be superimposed onthe profile of the B, owing to the diffusion of C which can occur duringthe RTA process required for complete activation of the B, in otherwords RTA for 30 seconds at 900° C. This superimposition can severelyimpair the electrical properties of the junction. FIG. 3 shows the Cprofiles before and after SPE, and after SPE and RTA at 900° C., andcompared with the B profile after SPE and RTA at 900° C. The SPE processleaves the C profile virtually unaltered, while a diffusion tail is seenin the silicon covering layer after 30 seconds at 900° C. This tailstarts at a concentration level of approximately 2×10 ¹⁸/cm³ and fallsto the SIMS base level of 2×10¹⁷/cm³ at a depth of approximately 120 nm.Consequently, the C diffusing to the outside of the carbon-rich layerwill certainly be superimposed on the B profile, but well below theconcentration level of 2×10¹⁷/cm³, in other words less by more than anorder of magnitude than the concentration of C used by P. A. Stolk etal. [Stolk 95]. It should be emphasized that the significant surfacepeak of C with a pronounced tail does not correspond to a realcontamination of C in the substance.

In fact, it is a well-known SIMS artefact, produced during analysis bythe relocation, by sputtering beam, of the C contamination which isalways present on the surface of Si exposed to air. Similarconsiderations apply to the deeper interface of the carbon-rich layerwhich is artificially widened exponentially towards the substrate by theaction of the sputtering beam. In fact, the exponential decay of thisinterface has the same slope as the characteristic found at the surface.It can therefore be concluded that, after 30 seconds at 900° C., theboron is totally active without any TED, and moreover the carbon layerremains well separated spatially from the dopant.

In conclusion, the experiment demonstrates that the crystalline natureof the material can be recovered fully and the dopant can be activatedcompletely with total suppression of TED, by introducing a C-richsilicon layer between the boron implanted in pre-amorphized silicon andthe EOR damage. This method can therefore be considered for thefabrication of ultra-shallow junctions for future generations ofdevices.

In particular, the process according to the invention provides thefollowing advantages:

-   a) owing to the complete suppression of TED, the diffusion of the    dopant throughout the process is simply the equilibrium diffusion,    which can be modelled conventionally and controlled to keep it at    negligible levels. With this method, the dopant profile can be    controlled, for example, simply by varying the implantation energy    and dose, without any post-implantation diffusion.-   b) The method can be used to form shallower junctions than those    formed by the present methods.-   c) The method can be used to create lateral profiles of active    dopant which are sharper than those which can be obtained by present    technology, thus permitting better control of the gate width of CMOS    devices, and particularly narrower gates.-   d) This method could be used to produce present-day devices, such as    those to be produced in the near future, by using higher    implantation energies and therefore with greater efficiency and    lower costs.-   e) Theoretically, this method could make it possible, by using    modern industrial implanters capable of implanting boron with an    energy of up to 0.2 keV, to form junctions with depths of less than    15 nm, as required for the 0.04 μm technological node in 2011. The    importance of this result will be understood when it is realized    that no methods are yet known for forming source/drain junctions for    CMOS devices even for the 0.09 μm node in 2004.-   f) Since the element acting as the trap is kept spatially separate    from the doped region, all problems relating to the dopant-trap    interaction are eliminated, particularly the electrical inactivation    of the dopant due to the formation of agglomerates between the    dopant and the trap element. Problems relating to the presence of    the trap element in the active region, for example the degradation    of the electrical properties of the silicon and the junction, are    also eliminated.

REFERENCES

-   [Road] International Technology Roadmap for Semiconductors    (Semiconductor Industry Association, Austin, Tex., 2000).-   [Stolk 95] P. A. Stolk, D. J. Eaglesham, H.-J. Gossmann, J. M.    Poate, Appl. Phys. Lett. 66, 1370 (1995).-   [Stolk 97] P. A. Stolk, H.-J. Gossmann, D. J. Eaglesham, D. C.    Jacobson, C. S. Rafferty, G. H. Gilmer, M. Jaraiz, J. M.    Poate, H. S. Luftman and T. E. Haynes, J. Appl. Phys. 81, 6031(1997)    and indicated references.-   [Stolk 01] P. A. Stolk “Shallow p-type junctions for sub-100 nm    CMOS”, Dissertation presented at MRS Spring Meeting 2001, San    Francisco 16-20 Apr. 2001-   [Napolitani] E. Napolitani, A. Carnera, E. Schroer, V.    Pri-vitera, F. Priolo, S. Moffatt, Appl. Phys. Lett. 75, 1869    (1999).-   [Jones] K. S. Jones, L. H. Zhang, V. Krishnamoorthy, M. Law, D. S.    Simons, P. Chi, L. Rubin, R. G. Elliman, Appl. Phys. Lett. 68, 2672    (1996).-   [Robertson] L. S. Robertson, M. E. Law, K. S. Jones, L. M. Rubin, J.    Jackson, P. Chi, D. S. Simons, Appl. Phys. Lett. 75, 3844 (1999).-   [Ban] I. Ban, M. Öztürk, K. Christensen, D. M. Maher, Appl. Phys.    Lett. 68, 499 (1996).-   [Priolo] F. Priolo, G. Mannino, M. Miccichè, V. Privitera, E.    Napolitani, A. Carnera, Appl. Phys. Lett. 72, 3011 (1998).

1. Method for suppressing transient enhanced diffusion (TED) of a dopantimplanted in a thin surface layer of a semiconductor substrate, causedby the interaction between the dopant and the lattice damage produced bythe implantation during the thermal process of post-implantationannealing, characterized in that the aforesaid thermal process iscarried out on a crystalline semiconductor provided with an amorphoussurface layer in which the said dopant is implanted and which has alayer rich in a trap element which effective traps self-interstitialpoint defects, the layer being spatially separated from the dopant-richsurface layer and interposed between said dopant-rich surface layer andthe interface between the amorphous and crystalline regions of thesubstrate.
 2. Method according to claim 1, in which the amorphous layeris produced by ion implantation in the crystalline substrate.
 3. Methodaccording to claim 2, in which the layer rich in the trap element,spatially separate from the dopant-rich layer, is produced by depositionbefore or after the amorphization implantation.
 4. Method according toclaim 2, in which the layer rich in the trap element is produced by ionimplantation before or after the amorphization implantation.
 5. Methodaccording to claim 1, in which the amorphous layer is produced bydeposition of amorphous silicon on the crystalline substrate.
 6. Methodaccording to claim 5, in which the layer rich in the trap element isproduced by ion implantation after the deposition of the amorphouslayer.
 7. Method according to claim 5, in which the layer rich in thetrap element is produced by deposition during the deposition of theamorphous layer.
 8. Method according to claim 1, in which thedopant-rich surface layer, having a thickness less than the thickness ofthe amorphous layer, is produced by ion implantation of the dopantbefore or after the formation of the amorphous layer.
 9. Methodaccording to claim 1, in which the trap element is carbon.
 10. Methodaccording to claim 9, in which the said layer rich in the trap elementcomprises carbon at a concentration ranging from 1×1018/cm3 to1×1021/cm3.
 11. Method according to claim 1, comprising the operationsof: a) growing a layer of carbon-rich silicon on the crystallinesemiconductor substrate, b) covering the layer produced at a) with alayer of silicon, c) amorphizing a surface layer at a depth greater thanthe depth of the carbon-rich layer, d) ion implantation of a dopant in athin surface layer having a depth such that the dopant layer isspatially separated from the carbon-rich layer, and e) applyingannealing heat treatment or a sequence of annealing heat treatments. 12.Method according to claim 1, in which the heat treatment or at leastpart thereof is carried out in conditions such that the amorphous layeris recrystallized.
 13. Method according to claim 12, in which the heattreatment is carried out in conditions such that the dopant iselectrically activated.
 14. Method according to claim 1, in which theheat treatment or part thereof is carried out in such a way that nosignificant superimposition is caused between the dopant and the trapelement.
 15. Process for forming a shallow doped region in asemiconductor, comprising the operations of: implanting a dopant in athin surface layer of the semiconductor and carrying out one or moreheat treatments to reconstruct the crystalline structure of thesemiconductor and/or to electrically activate the dopant, characterizedin that the aforesaid heat treatments are applied to a crystallinesemiconductor having an amorphous surface layer, in which the saiddopant is implanted, and also having a layer rich in a trap elementcapable of trapping self-interstitial point defects, this layer beingspatially separated from the dopant-rich surface layer and interposedbetween the said dopant-rich surface layer and the interface between theamorphous and crystalline regions of the substrate.
 16. Processaccording to claim 15, in which the amorphous layer is produced by ionimplantation in the crystalline substrate.
 17. Process according toclaim 16, in which the layer rich in the trap element, spatiallyseparate from the dopant-rich layer, is produced by deposition before orafter the amorphization implantation.
 18. Process according to claim 16,in which the layer rich in the trap element is produced by ionimplantation before or after the amorphization implantation.
 19. Processaccording to claim 15, in which the amorphous layer is produced bydeposition of amorphous silicon on the crystalline substrate. 20.Process according to claim 19, in which the layer rich in the trapelement is produced by ion implantation after the deposition of theamorphous layer.
 21. Process according to claim 19, in which the layerrich in the trap element is produced by deposition during the depositionof the amorphous layer.
 22. Process according to claim 15, in which thedopant-rich surface layer, having a thickness less than the thickness ofthe amorphous layer, is produced by ion implantation of the dopantbefore or after the formation of the amorphous layer.
 23. Processaccording to claim 15, in which the trap element is carbon.
 24. Processaccording to claim 23, in which the said layer rich in the trap elementcomprises carbon at a concentration ranging from 1×1018/cm3 to1×1021/cm3.
 25. Process according to claim 15, comprising the operationsof: a) growing a layer of carbon-rich silicon on the crystallinesemiconductor substrate, b) covering the layer produced at a) with alayer of silicon, c) amorphizing a surface layer by ion implantation ata depth greater than the depth of the carbon-rich layer, d) ionimplantation of a dopant in a thin surface layer having a depth suchthat the dopant layer is spatially separated from the carbon-rich layer,and e) applying annealing heat treatment or a sequence of annealing heattreatments.
 26. Process according to claim 15, in which the heattreatment or at least part thereof is carried out in conditions suchthat the amorphous layer is recrystallized.
 27. Process according toclaim 26, in which the heat treatment is carried out in conditions suchthat the dopant is electrically activated.
 28. Process according toclaim 15, in which the heat treatment or part thereof is carried out insuch a way that no significant superimposition is caused between thedopant and the trap element.
 29. Semiconductor device which can beproduced by a process according to claim
 15. 30. Intermediatesemiconductor device having a thin surface layer in which a dopant isimplanted and designed to be subjected to annealing heat treatments toreconstruct the crystalline structure of the semiconductor and/or toelectrically activate the dopant, characterized in that the saidintermediate device comprises a crystalline semiconductor with anamorphous surface layer, in which is implanted the said dopant, and acarbon-rich layer which is spatially separated from the dopant-richsurface layer and is interposed between the said surface layer and theinterface between the amorphous and crystalline regions of thesubstrate.